如何在VHDL中声明输出数组？-HowtodeclareoutputarrayinVHDL?

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If you want to declare a new type of an array for use on module output, thus not use some existing array type like std_logic_vector, then the type must be declared in a package, in order to make the type available where the module is instantiated. Example below:

如果要声明一个新类型的数组以用于模块输出，因此不使用某些现有数组类型（如std_logic_vector），则必须在包中声明该类型，以使类型可用于实例化模块的位置。示例如下：

library ieee;
use ieee.std_logic_1164.all;

package pkg is
  type slv8_array_t is array (natural range <>) of std_logic_vector(7 downto 0);
end package;

package body pkg is
end package body;


library ieee;
use ieee.std_logic_1164.all;
library work;
use work.pkg.all;

entity mdl is
  port(
    array_o : out slv8_array_t(0 to 3));
end entity;

architecture syn of mdl is
begin
  array_o <= (others => (others => '0'));
end architecture;

A similar approach applies to other declared types, like for example records, or for other kind of interface type sharing like input.

类似的方法适用于其他声明的类型，例如记录，或其他类型的接口类型共享，如输入。