FPGATESTBENCH读取文件数据

FPGA TESTBENCH读取文件数据

&＃96;timescale 1ns / 1ps// Company: 
// Engineer:
//
// Create Date:   13:44:03 12/09/2020
// Design Name:   Fir_Filt_top
// Module Name:   E:/FPGA_CODE/source/Fir_Filt_top_TB.v
// Project Name:  FIR_FILTER_TOP
// Target Device:  
// Tool versions:  
// Description: 
//
// Verilog Test Fixture created by ISE for module: Fir_Filt_top
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// module Fir_Filt_top_TB;// Inputsreg I_clk;reg I_rst;reg I_raw_data_vld;reg [15:0] I_raw_data;// Outputswire [31:0] O_float_dout;// Instantiate the Unit Under Test (UUT)Fir_Filt_top uut (.I_clk(I_clk), .I_rst(I_rst), .I_raw_data_vld(I_raw_data_vld), .I_raw_data(I_raw_data), .O_float_dout(O_float_dout));parameter  MemLen    &＃61; 512;        // 512 * 1reg [15 : 00] mem_raw_data [0 : MemLen];reg Start_flag &＃61; 0;integer index &＃61; 0;integer  j &＃61; 0;initial begin// Initialize InputsI_clk &＃61; 0;I_rst &＃61; 1;I_raw_data_vld &＃61; 0;I_raw_data &＃61; 0;Start_flag &＃61; 0;// Wait 100 ns for global reset to finish#1000; I_rst &＃61; 0;#1000; Start_flag &＃61; 1;// Add stimulus hereendinitial begin$readmemh ( "E:/Aligei_WaveMeter/FPGA_CODE/Algorithm/ST/Algo_Design/FIR_filter_demo/FIR_FILTER_TOP/source/raw_data.dat", mem_raw_data, 0, MemLen);endinitial begin#2000; while(1)beginj &＃61; j &＃43; 1;if((j>&＃61;10) & (j <&＃61; 521))beginindex &＃61; index &＃43; 1;I_raw_data_vld &＃61; 1;I_raw_data &＃61; mem_raw_data[index-1];            endelse if(j &＃61;&＃61; 522)beginI_raw_data_vld &＃61; 0;index &＃61; 0;endelse if(j &＃61;&＃61; 530)beginj &＃61; 0;end#10;endendalways #5 I_clk &＃61; ~I_clk;//    reg [31:00] index &＃61; 0;
//    reg [31:00] j &＃61; 0;endmodule