Makefile通用目标规则

我正在尝试改进天真的解决方案(用于编译目标的单个规则和用于将所有先前目标链接在一起的附加规则),我使用了我的makefile.我想出了以下Makefile(剪辑):

.PHONY: clean

BASE_DIR = ../

CC = gcc
CROSS_COMPILE = arm-none-eabi-
CFLAGS =-g -I${BASE_DIR}/include 
LDFLAGS =-L${BASE_DIR}/lib -Ttarget.ld -nostdlib 

SOURCES = first.c second.c third.c fourth.c
OBJECTS = $(SOURCES:.c=.o)
EXECUTABLE = $(OBJECTS:.o=)

all: $(EXECUTABLE)

%:
    ${CROSS_COMPILE}$(CC) $(CFLAGS) $(LDFLAGS) $*.c -o $*

clean:
    rm ${EXECUTABLE}

这工作正常,但我想分开编译和链接过程.因此我尝试将其修改如下:

.PHONY: clean

BASE_DIR = ../

CC = gcc
CROSS_COMPILE = arm-none-eabi-

CFLAGS =-c -g -I${BASE_DIR}/include 
LDFLAGS =-L${BASE_DIR}/lib -Ttarget.ld -nostdlib 

SOURCES = first.c second.c third.c fourth.c
OBJECTS = $(SOURCES:.c=.o)
EXECUTABLE = $(OBJECTS:.o=)

all : $(EXECUTABLE)

%.o : %.c
    @echo "Compiling c file into o file"
    ${CROSS_COMPILE}$(CC) $(CFLAGS) $< -o $@

% : %.o
    @echo "Linking o file into executable"
    ${CROSS_COMPILE}$(CC) $(LDFLAGS) $< -o $@

clean:
    rm ${EXECUTABLE}

这工作正常然后我调用Makefile作为例如make first.o; make first或如果我修改EXECUTABLE = $(OBJECTS:.o=)to EXECUTABLE = $(OBJECTS:.o=.out)和% : %.oto %.out : %.o.但是,如果我尝试调用编译make或make first使用隐式规则.

我尝试过Makefile手册,但那里确实有很多信息,我有点困惑.

如何修改Makefile以允许同时调用构建单独的目标作为make 或所有目标make？